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authorGreg Ungerer <gerg@uclinux.org>2009-03-24 16:50:09 +1000
committerGreg Ungerer <gerg@uclinux.org>2009-03-24 16:50:09 +1000
commitde1fc5c629f1597ddc996379642f9f3594dcdfbe (patch)
tree2b3bd1bb9a2116e3ae44d032321b5bbb42c00e84 /arch/m68knommu
parent4ce2cba45a46668409606bdb9923164b51986807 (diff)
downloadlinux-de1fc5c629f1597ddc996379642f9f3594dcdfbe.tar.bz2
m68knommu: fix 5249 ColdFire UART setup
The ICR registers of the 5249 ColdFire processor are 8bits, not 32bits. Fix the read/write of these register to be the correct size. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/5249/config.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 9c926dedb7c2..3b808c64e671 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -51,11 +51,11 @@ static struct platform_device *m5249_devices[] __initdata = {
static void __init m5249_uart_init_line(int line, int irq)
{
if (line == 0) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
} else if (line == 1) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
}