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authorGreg Ungerer <gerg@uclinux.org>2009-03-24 17:33:41 +1000
committerGreg Ungerer <gerg@uclinux.org>2009-03-24 17:38:11 +1000
commit522b3d49179a0d2dc4e152b77eb82fbfe97782f4 (patch)
treeb92f7a5ab66575b7af4160143adbfe962ec1e1f6 /arch/m68knommu
parent9242ef12f0d174da1739a071fb4a5fc5de27905e (diff)
downloadlinux-522b3d49179a0d2dc4e152b77eb82fbfe97782f4.tar.bz2
m68knommu: fix 5407 ColdFire UART vector setup
There is a couple of problems with the UART vector setup for the 5307 ColdFire UART. The ICR register access should be 8bit, not 32bit. The address of the UIVR register is wrong, it needs to be offset into the MBAR register region. Fix these. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68knommu')
-rw-r--r--arch/m68knommu/platform/5407/config.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index 648b8b778211..0ee8c1a200c8 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -56,12 +56,12 @@ static struct platform_device *m5407_devices[] __initdata = {
static void __init m5407_uart_init_line(int line, int irq)
{
if (line == 0) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
- writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+ writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
} else if (line == 1) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
- writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+ writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
}
}