diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2011-12-24 12:40:37 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-03-05 09:43:09 +1000 |
| commit | 6c84a60eb98911cb376cf0a340f811401f3b29a4 (patch) | |
| tree | 8abd882ad56da22ef4d796e88857a30bf8d08af5 /arch/m68k | |
| parent | 2424f549020b6f87ea3b6e89fd7bd26ddf1f717b (diff) | |
| download | linux-6c84a60eb98911cb376cf0a340f811401f3b29a4.tar.bz2 | |
m68knommu: make 527x QSPI platform addressing consistent
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire
family members then we will be able to remove the duplicated plaform data
and code and use a single setup for all.
So modify the ColdFire 527x QSPI addressing so that:
. base addresses are absolute (not relative to MBAR peripheral register)
. use a common name for IRQs used
. move chip select definitions (CS) to appropriate header
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k')
| -rw-r--r-- | arch/m68k/include/asm/m527xsim.h | 24 | ||||
| -rw-r--r-- | arch/m68k/include/asm/mcfqspi.h | 2 | ||||
| -rw-r--r-- | arch/m68k/platform/527x/config.c | 20 |
3 files changed, 29 insertions, 17 deletions
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 59bb776a5e3c..f1c5b2c8d447 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -59,6 +59,8 @@ #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -103,6 +105,28 @@ #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) #define MCFFEC_SIZE1 0x800 +/* + * QSPI module. + */ +#define MCFQSPI_BASE (MCF_IPSBAR + 0x340) +#define MCFQSPI_SIZE 0x40 + +#ifdef CONFIG_M5271 +#define MCFQSPI_CS0 91 +#define MCFQSPI_CS1 92 +#define MCFQSPI_CS2 99 +#define MCFQSPI_CS3 103 +#endif +#ifdef CONFIG_M5275 +#define MCFQSPI_CS0 59 +#define MCFQSPI_CS1 60 +#define MCFQSPI_CS2 61 +#define MCFQSPI_CS3 62 +#endif + +/* + * GPIO module. + */ #ifdef CONFIG_M5271 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index e9a7e1a2c995..57fcbc2c0dac 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -21,7 +21,7 @@ #ifndef mcfqspi_h #define mcfqspi_h -#if defined(CONFIG_M527x) || defined(CONFIG_M528x) +#if defined(CONFIG_M528x) #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) #elif defined(CONFIG_M532x) #define MCFQSPI_IOBASE 0xFC058000 diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c index 018ac69ef242..e86ff3a0ba15 100644 --- a/arch/m68k/platform/527x/config.c +++ b/arch/m68k/platform/527x/config.c @@ -29,29 +29,17 @@ #if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) static struct resource m527x_qspi_resources[] = { { - .start = MCFQSPI_IOBASE, - .end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1, + .start = MCFQSPI_BASE, + .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1, .flags = IORESOURCE_MEM, }, { - .start = MCFINT_VECBASE + MCFINT_QSPI, - .end = MCFINT_VECBASE + MCFINT_QSPI, + .start = MCF_IRQ_QSPI, + .end = MCF_IRQ_QSPI, .flags = IORESOURCE_IRQ, }, }; -#if defined(CONFIG_M5271) -#define MCFQSPI_CS0 91 -#define MCFQSPI_CS1 92 -#define MCFQSPI_CS2 99 -#define MCFQSPI_CS3 103 -#elif defined(CONFIG_M5275) -#define MCFQSPI_CS0 59 -#define MCFQSPI_CS1 60 -#define MCFQSPI_CS2 61 -#define MCFQSPI_CS3 62 -#endif - static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control) { int status; |