diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2011-12-24 00:46:37 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2012-03-05 09:43:06 +1000 |
| commit | bbbeeaf2f74b634c95af3492e4958e752966eaa5 (patch) | |
| tree | 1cddb9bdf8d1e7ed123f70205927692463c35c5f /arch/m68k/include | |
| parent | 69d23b610a04e269d6a094e6f3e37d85d6b2784a (diff) | |
| download | linux-bbbeeaf2f74b634c95af3492e4958e752966eaa5.tar.bz2 | |
m68knommu: make 54xx UART platform addressing consistent
If we make all UART addressing consistent across all ColdFire family members
then we will be able to remove the duplicated plaform data and use a single
setup for all.
So modify the ColdFire 54xx UART addressing so that:
. UARTs are numbered from 0 up
. base addresses are absolute (not relative to MBAR peripheral register)
. use a common name for IRQs used
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/m54xxsim.h | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 1ed8bfb02772..ae56b8848a9d 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -31,16 +31,20 @@ /* * UART module. */ -#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ -#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ -#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ -#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ +#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ +#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ /* * Define system peripheral IRQ usage. */ -#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ -#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ +#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ +#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) +#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) /* * Generic GPIO support |