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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2019-06-24 19:38:30 +0200 |
|---|---|---|
| committer | Herbert Xu <herbert@gondor.apana.org.au> | 2019-07-03 22:13:12 +0800 |
| commit | e217413964a453fc2eeb437c32deb00581cf899d (patch) | |
| tree | fbb70df97290e79cda11c63bbec4506e0ae1f00e /arch/m68k/ifpsp060/iskeleton.S | |
| parent | d45b1714e25e39b94df3da10ba8e95e63865b278 (diff) | |
| download | linux-e217413964a453fc2eeb437c32deb00581cf899d.tar.bz2 | |
crypto: arm64/aes-ce - add 5 way interleave routines
In preparation of tweaking the accelerated AES chaining mode routines
to be able to use a 5-way stride, implement the core routines to
support processing 5 blocks of input at a time. While at it, drop
the 2 way versions, which have been unused for a while now.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'arch/m68k/ifpsp060/iskeleton.S')
0 files changed, 0 insertions, 0 deletions