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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 16:36:14 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 16:36:14 +0800 |
| commit | b61a40afca164a9bd066f749beff3bf209c5e209 (patch) | |
| tree | 414693038d707d37b34edfee4f4ece650275996a /arch/loongarch/kernel/traps.c | |
| parent | a2a84e36331af3b000ad12b552c5485b8282b366 (diff) | |
| download | linux-b61a40afca164a9bd066f749beff3bf209c5e209.tar.bz2 | |
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/kernel/traps.c')
| -rw-r--r-- | arch/loongarch/kernel/traps.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c index 5010e95cef84..a5e8bd5d7948 100644 --- a/arch/loongarch/kernel/traps.c +++ b/arch/loongarch/kernel/traps.c @@ -620,9 +620,6 @@ asmlinkage void noinstr do_vint(struct pt_regs *regs, unsigned long sp) irqentry_exit(regs, state); } -extern void tlb_init(int cpu); -extern void cache_error_setup(void); - unsigned long eentry; unsigned long tlbrentry; |