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author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-16 11:22:45 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-04-16 11:22:45 -0700 |
commit | 7d38cc02909b85f6f4d3f082c471f0151fc5be3e (patch) | |
tree | cb352bf442ed28f223e7061d9265a79c02fca6db /arch/ia64 | |
parent | 10ec34fcb100412ab186c141a9c3557d1270effd (diff) | |
parent | c0b5a64d937f8fff79b10410a8a70ecaa9a1c580 (diff) | |
download | linux-7d38cc02909b85f6f4d3f082c471f0151fc5be3e.tar.bz2 |
Merge tag 'please-pull-ia64-erratum' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux
Pull itanium erratum fix from Tony Luck:
"Small workaround for a rare, but annoying, erratum #237"
* tag 'please-pull-ia64-erratum' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux:
[IA64] Change default PSR.ac from '1' to '0' (Fix erratum #237)
Diffstat (limited to 'arch/ia64')
-rw-r--r-- | arch/ia64/kernel/head.S | 2 | ||||
-rw-r--r-- | arch/ia64/kernel/ivt.S | 2 | ||||
-rw-r--r-- | arch/ia64/kvm/vmm_ivt.S | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S index e6f80fcf013b..a4acddad0c78 100644 --- a/arch/ia64/kernel/head.S +++ b/arch/ia64/kernel/head.S @@ -259,7 +259,7 @@ start_ap: * Switch into virtual mode: */ movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \ - |IA64_PSR_DI|IA64_PSR_AC) + |IA64_PSR_DI) ;; mov cr.ipsr=r16 movl r17=1f diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S index 689ffcaa284e..18e794a57248 100644 --- a/arch/ia64/kernel/ivt.S +++ b/arch/ia64/kernel/ivt.S @@ -58,7 +58,7 @@ #include <asm/unistd.h> #include <asm/errno.h> -#if 1 +#if 0 # define PSR_DEFAULT_BITS psr.ac #else # define PSR_DEFAULT_BITS 0 diff --git a/arch/ia64/kvm/vmm_ivt.S b/arch/ia64/kvm/vmm_ivt.S index 24018484c6e9..397e34a63e18 100644 --- a/arch/ia64/kvm/vmm_ivt.S +++ b/arch/ia64/kvm/vmm_ivt.S @@ -64,7 +64,7 @@ #include "kvm_minstate.h" #include "vti.h" -#if 1 +#if 0 # define PSR_DEFAULT_BITS psr.ac #else # define PSR_DEFAULT_BITS 0 |