diff options
author | Adrian Bunk <bunk@stusta.de> | 2006-12-07 02:14:19 +0100 |
---|---|---|
committer | Andi Kleen <andi@basil.nowhere.org> | 2006-12-07 02:14:19 +0100 |
commit | d9408cefe677636bc1c100fdcfac0b2ab9ff87bf (patch) | |
tree | 5f042bdcea216867e93d38d12decfd66e4612a2d /arch/i386 | |
parent | b65780e123ba9b762276482bbfb52836e4d41fd9 (diff) | |
download | linux-d9408cefe677636bc1c100fdcfac0b2ab9ff87bf.tar.bz2 |
[PATCH] i386: Clean up smp_tune_scheduling()
- remove the write-only local variable "bandwidth"
- don't set "max_cache_size" in the (cachesize < 0) case:
that's already handled in kernel/sched.c:measure_migration_cost()
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Diffstat (limited to 'arch/i386')
-rw-r--r-- | arch/i386/kernel/smpboot.c | 29 |
1 files changed, 5 insertions, 24 deletions
diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c index 346f27f4c79f..b4e6f32de453 100644 --- a/arch/i386/kernel/smpboot.c +++ b/arch/i386/kernel/smpboot.c @@ -1130,34 +1130,15 @@ exit: } #endif -static void smp_tune_scheduling (void) +static void smp_tune_scheduling(void) { unsigned long cachesize; /* kB */ - unsigned long bandwidth = 350; /* MB/s */ - /* - * Rough estimation for SMP scheduling, this is the number of - * cycles it takes for a fully memory-limited process to flush - * the SMP-local cache. - * - * (For a P5 this pretty much means we will choose another idle - * CPU almost always at wakeup time (this is due to the small - * L1 cache), on PIIs it's around 50-100 usecs, depending on - * the cache size) - */ - if (!cpu_khz) { - /* - * this basically disables processor-affinity - * scheduling on SMP without a TSC. - */ - return; - } else { + if (cpu_khz) { cachesize = boot_cpu_data.x86_cache_size; - if (cachesize == -1) { - cachesize = 16; /* Pentiums, 2x8kB cache */ - bandwidth = 100; - } - max_cache_size = cachesize * 1024; + + if (cachesize > 0) + max_cache_size = cachesize * 1024; } } |