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| author | Guo Ren <ren_guo@c-sky.com> | 2019-07-30 14:08:07 +0800 |
|---|---|---|
| committer | Guo Ren <ren_guo@c-sky.com> | 2019-07-31 11:04:29 +0800 |
| commit | 81b23ba645e6b2b446093b2d927c261a17f7dee3 (patch) | |
| tree | 2f2b5cbb6afd1653fd4ac1ef330d05f8b84b3a06 /arch/csky | |
| parent | 609488bc979f99f805f34e9a32c1e3b71179d10b (diff) | |
| download | linux-81b23ba645e6b2b446093b2d927c261a17f7dee3.tar.bz2 | |
csky: Fixup mb() synchronization problem
The mb() is the superset of dma and smp. Using bar.xxx to implement
mb() will cause problem when sync data with dma device, becasue
bar.xxx couldn't guarantee bus transactions finished at outside bus
level.
We must use sync.s instead of bar.xxx for dma data synchronization
and it will guarantee retirement after getting the bus bresponse.
Changes for V2:
- Use sync.s for all mb, rmb, wmb, dma_wmb, dma_rmb.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky')
| -rw-r--r-- | arch/csky/include/asm/barrier.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/arch/csky/include/asm/barrier.h b/arch/csky/include/asm/barrier.h index 476eb786f22d..a430e7fddf35 100644 --- a/arch/csky/include/asm/barrier.h +++ b/arch/csky/include/asm/barrier.h @@ -9,11 +9,12 @@ #define nop() asm volatile ("nop\n":::"memory") /* - * sync: completion barrier - * sync.s: completion barrier and shareable to other cores - * sync.i: completion barrier with flush cpu pipeline - * sync.is: completion barrier with flush cpu pipeline and shareable to - * other cores + * sync: completion barrier, all sync.xx instructions + * guarantee the last response recieved by bus transaction + * made by ld/st instructions before sync.s + * sync.s: inherit from sync, but also shareable to other cores + * sync.i: inherit from sync, but also flush cpu pipeline + * sync.is: the same with sync.i + sync.s * * bar.brwarw: ordering barrier for all load/store instructions before it * bar.brwarws: ordering barrier for all load/store instructions before it @@ -27,9 +28,7 @@ */ #ifdef CONFIG_CPU_HAS_CACHEV2 -#define mb() asm volatile ("bar.brwarw\n":::"memory") -#define rmb() asm volatile ("bar.brar\n":::"memory") -#define wmb() asm volatile ("bar.bwaw\n":::"memory") +#define mb() asm volatile ("sync.s\n":::"memory") #ifdef CONFIG_SMP #define __smp_mb() asm volatile ("bar.brwarws\n":::"memory") |