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authorGuo Ren <ren_guo@c-sky.com>2019-07-30 17:16:28 +0800
committerGuo Ren <ren_guo@c-sky.com>2019-08-06 15:15:34 +0800
commitae76f635d4e1cffa6870cc5472567ca9d6940a22 (patch)
treeb2eb9bedbf954e9301722f1cad5ddd7c426021a8 /arch/csky/mm/cachev1.c
parent4af9027d3f4061992c0b065102a0a666b72f073b (diff)
downloadlinux-ae76f635d4e1cffa6870cc5472567ca9d6940a22.tar.bz2
csky: Optimize arch_sync_dma_for_cpu/device with dma_inv_range
DMA_FROM_DEVICE only need to read dma data of memory into CPU cache, so there is no need to clear cache before. Also clear + inv for DMA_FROM_DEVICE won't cause problem, because the memory range for dma won't be touched by software during dma working. Changes for V2: - Remove clr cache and ignore the DMA_TO_DEVICE in _for_cpu. - Change inv to wbinv cache with DMA_FROM_DEVICE in _for_device. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/mm/cachev1.c')
-rw-r--r--arch/csky/mm/cachev1.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/csky/mm/cachev1.c b/arch/csky/mm/cachev1.c
index b8a75cce0b8c..494ec912abff 100644
--- a/arch/csky/mm/cachev1.c
+++ b/arch/csky/mm/cachev1.c
@@ -120,7 +120,12 @@ void dma_wbinv_range(unsigned long start, unsigned long end)
cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
}
+void dma_inv_range(unsigned long start, unsigned long end)
+{
+ cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
+}
+
void dma_wb_range(unsigned long start, unsigned long end)
{
- cache_op_range(start, end, DATA_CACHE|CACHE_INV, 1);
+ cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1);
}