diff options
| author | Robert P. J. Day <rpjday@mindspring.com> | 2007-10-19 23:10:43 +0200 |
|---|---|---|
| committer | Adrian Bunk <bunk@kernel.org> | 2007-10-19 23:10:43 +0200 |
| commit | 3a4fa0a25da81600ea0bcd75692ae8ca6050d165 (patch) | |
| tree | a4de1662e645c029cf3cf58f0646cbb1959861dc /arch/cris | |
| parent | 18735dd8d2d37031b97f9e9e106acbaed01eb896 (diff) | |
| download | linux-3a4fa0a25da81600ea0bcd75692ae8ca6050d165.tar.bz2 | |
Fix misspellings of "system", "controller", "interrupt" and "necessary".
Fix the various misspellings of "system", controller", "interrupt" and
"[un]necessary".
Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'arch/cris')
| -rw-r--r-- | arch/cris/arch-v10/drivers/pcf8563.c | 2 | ||||
| -rw-r--r-- | arch/cris/arch-v32/drivers/pcf8563.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c index 1de0026bb94e..c263b8232dbc 100644 --- a/arch/cris/arch-v10/drivers/pcf8563.c +++ b/arch/cris/arch-v10/drivers/pcf8563.c @@ -4,7 +4,7 @@ * From Phillips' datasheet: * * The PCF8563 is a CMOS real-time clock/calendar optimized for low power - * consumption. A programmable clock output, interupt output and voltage + * consumption. A programmable clock output, interrupt output and voltage * low detector are also provided. All address and data are transferred * serially via two-line bidirectional I2C-bus. Maximum bus speed is * 400 kbits/s. The built-in word address register is incremented diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c index da479a14f836..6dbd700d3d66 100644 --- a/arch/cris/arch-v32/drivers/pcf8563.c +++ b/arch/cris/arch-v32/drivers/pcf8563.c @@ -4,7 +4,7 @@ * From Phillips' datasheet: * * The PCF8563 is a CMOS real-time clock/calendar optimized for low power - * consumption. A programmable clock output, interupt output and voltage + * consumption. A programmable clock output, interrupt output and voltage * low detector are also provided. All address and data are transferred * serially via two-line bidirectional I2C-bus. Maximum bus speed is * 400 kbits/s. The built-in word address register is incremented |