diff options
| author | Sonic Zhang <sonic.zhang@analog.com> | 2012-05-15 13:04:24 +0800 |
|---|---|---|
| committer | Bob Liu <lliubbo@gmail.com> | 2012-05-21 14:54:57 +0800 |
| commit | 8bf7135fff46f6ac28baf28a8e4144f685b456a0 (patch) | |
| tree | f769648ea45a40a73775baad38c2756ca2176e73 /arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h | |
| parent | 5a84775e999a5579e10f7297776c71b0be2ebd74 (diff) | |
| download | linux-8bf7135fff46f6ac28baf28a8e4144f685b456a0.tar.bz2 | |
blackfin: bf60x: Rename the DDR controller macro
Rename the DDR controller macro from DDR0 to DMC0 to avoid confustion for
bf60x.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat (limited to 'arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h')
| -rw-r--r-- | arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h index 88a05264ebda..4954cf3f7e16 100644 --- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h @@ -298,24 +298,24 @@ #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val) /* DDR2 Memory Control Registers */ -#define bfin_read_DDR0_CFG() bfin_read32(DDR0_CFG) -#define bfin_write_DDR0_CFG(val) bfin_write32(DDR0_CFG, val) -#define bfin_read_DDR0_TR0() bfin_read32(DDR0_TR0) -#define bfin_write_DDR0_TR0(val) bfin_write32(DDR0_TR0, val) -#define bfin_read_DDR0_TR1() bfin_read32(DDR0_TR1) -#define bfin_write_DDR0_TR1(val) bfin_write32(DDR0_TR1, val) -#define bfin_read_DDR0_TR2() bfin_read32(DDR0_TR2) -#define bfin_write_DDR0_TR2(val) bfin_write32(DDR0_TR2, val) -#define bfin_read_DDR0_MR() bfin_read32(DDR0_MR) -#define bfin_write_DDR0_MR(val) bfin_write32(DDR0_MR, val) -#define bfin_read_DDR0_EMR1() bfin_read32(DDR0_EMR1) -#define bfin_write_DDR0_EMR1(val) bfin_write32(DDR0_EMR1, val) -#define bfin_read_DDR0_CTL() bfin_read32(DDR0_CTL) -#define bfin_write_DDR0_CTL(val) bfin_write32(DDR0_CTL, val) -#define bfin_read_DDR0_STAT() bfin_read32(DDR0_STAT) -#define bfin_write_DDR0_STAT(val) bfin_write32(DDR0_STAT, val) -#define bfin_read_DDR0_DLLCTL() bfin_read32(DDR0_DLLCTL) -#define bfin_write_DDR0_DLLCTL(val) bfin_write32(DDR0_DLLCTL, val) +#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG) +#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val) +#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0) +#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val) +#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1) +#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val) +#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2) +#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val) +#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR) +#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val) +#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1) +#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) +#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) +#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) +#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) +#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) +#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) +#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val) /* DDR BankRead and Write Count Registers */ |