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| author | Mike Frysinger <vapier@gentoo.org> | 2010-05-27 21:47:31 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-08-06 12:55:46 -0400 |
| commit | dc7101bbaed644e61aa0056ff572b8d7a58e1ef0 (patch) | |
| tree | 5fb562e5ab4fa556c37ea89f066c4a10cd1559e0 /arch/blackfin/mach-bf548 | |
| parent | 5369fba13611118bc380674a410bede0863566f2 (diff) | |
| download | linux-dc7101bbaed644e61aa0056ff572b8d7a58e1ef0.tar.bz2 | |
Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf548')
| -rw-r--r-- | arch/blackfin/mach-bf548/include/mach/anomaly.h | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 7d08c7524498..4070079e2c00 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -5,7 +5,7 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2009 Analog Devices Inc. + * Copyright 2004-2010 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ @@ -28,7 +28,7 @@ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */ +/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ #define ANOMALY_05000220 (1) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) @@ -210,10 +210,16 @@ #define ANOMALY_05000473 (1) /* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ #define ANOMALY_05000474 (1) -/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ -#define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) +/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ +#define ANOMALY_05000483 (1) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) +/* IFLUSH sucks at life */ +#define ANOMALY_05000491 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -229,6 +235,7 @@ #define ANOMALY_05000198 (0) #define ANOMALY_05000202 (0) #define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) #define ANOMALY_05000227 (0) #define ANOMALY_05000230 (0) #define ANOMALY_05000231 (0) @@ -263,5 +270,6 @@ #define ANOMALY_05000412 (0) #define ANOMALY_05000432 (0) #define ANOMALY_05000435 (0) +#define ANOMALY_05000475 (0) #endif |