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| author | Michael Hennerich <michael.hennerich@analog.com> | 2009-01-07 23:14:39 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2009-01-07 23:14:39 +0800 |
| commit | 73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff (patch) | |
| tree | 09fa1f153a2ca810ad72978736f85359205d64a3 /arch/blackfin/Kconfig | |
| parent | c97618d3b7b8ef86a966c4b67b54e5ca15814905 (diff) | |
| download | linux-73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff.tar.bz2 | |
Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option
- remove duplicated code and headers
- add option allowing arbitrary SDRAM/DDR Timing parameters.
- mark automatically calculated timings as EXPERIMENTAL
- fix comment header block
Related to BUGs:
- kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on.
- kernel does not boot if re-program clocks
[ Mike Frysinger <vapier.adi@gmail.com>
- fix comment header
- mark do_sync static
- document the DMA shutdown
- simplify SIC_IWR handling
- fix ANOMALY_05000265 handling to work as intended ]
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/Kconfig')
| -rw-r--r-- | arch/blackfin/Kconfig | 59 |
1 files changed, 57 insertions, 2 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index f8edfbe5faed..5f09d9349322 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -473,6 +473,61 @@ config MEM_MT46V32M16_5B bool "MT46V32M16_5B" endchoice +choice + prompt "DDR/SDRAM Timing" + depends on BFIN_KERNEL_CLOCK + default BFIN_KERNEL_CLOCK_MEMINIT_CALC + help + This option allows you to specify Blackfin SDRAM/DDR Timing parameters + The calculated SDRAM timing parameters may not be 100% + accurate - This option is therefore marked experimental. + +config BFIN_KERNEL_CLOCK_MEMINIT_CALC + bool "Calculate Timings (EXPERIMENTAL)" + depends on EXPERIMENTAL + +config BFIN_KERNEL_CLOCK_MEMINIT_SPEC + bool "Provide accurate Timings based on target SCLK" + help + Please consult the Blackfin Hardware Reference Manuals as well + as the memory device datasheet. + http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram +endchoice + +menu "Memory Init Control" + depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC + +config MEM_DDRCTL0 + depends on BF54x + hex "DDRCTL0" + default 0x0 + +config MEM_DDRCTL1 + depends on BF54x + hex "DDRCTL1" + default 0x0 + +config MEM_DDRCTL2 + depends on BF54x + hex "DDRCTL2" + default 0x0 + +config MEM_EBIU_DDRQUE + depends on BF54x + hex "DDRQUE" + default 0x0 + +config MEM_SDRRC + depends on !BF54x + hex "SDRRC" + default 0x0 + +config MEM_SDGCTL + depends on !BF54x + hex "SDGCTL" + default 0x0 +endmenu + config MAX_MEM_SIZE int "Max SDRAM Memory Size in MBytes" depends on !MPU @@ -1104,13 +1159,13 @@ config BFIN_CPU_FREQ config CPU_VOLTAGE bool "CPU Voltage scaling" - depends on EXPERIMENTAL + depends on EXPERIMENTAL depends on CPU_FREQ default n help Say Y here if you want CPU voltage scaling according to the CPU frequency. This option violates the PLL BYPASS recommendation in the Blackfin Processor - manuals. There is a theoretical risk that during VDDINT transitions + manuals. There is a theoretical risk that during VDDINT transitions the PLL may unlock. endmenu |