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| author | Michal Simek <monstr@monstr.eu> | 2010-04-26 13:43:23 +0200 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2010-05-06 11:21:59 +0200 |
| commit | 598acab44dcbda0e300d9d080e81566334138e7d (patch) | |
| tree | 19f8a929ce264068a21b25b91258afe4bad64b75 /arch/arm | |
| parent | 77543cebab7387eab7d482e90018a64d6f2ced1e (diff) | |
| download | linux-598acab44dcbda0e300d9d080e81566334138e7d.tar.bz2 | |
microblaze: Define correct L1_CACHE_SHIFT value
Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.
We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.
Here is the calculation for cacheline lenght 8 32bit=4Byte values
which is corresponding with SHIFT 5.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch/arm')
0 files changed, 0 insertions, 0 deletions