diff options
| author | Myron Stowe <mstowe@redhat.com> | 2012-02-07 15:26:44 -0700 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2012-02-21 09:35:32 +0000 |
| commit | e23e8c0690d2952dce53e712d01d5b2179f98b64 (patch) | |
| tree | df2533028276a094b2b38c5922b0cf6561e5d1eb /arch/arm | |
| parent | 910ba598c818243cf3de2f97e03c49948bbb0511 (diff) | |
| download | linux-e23e8c0690d2952dce53e712d01d5b2179f98b64.tar.bz2 | |
ARM/PCI: Remove ARM's duplicate definition of 'pcibios_max_latency'
The patch series to re-factor PCI's 'latency timer' setup (re:
http://marc.info/?l=linux-kernel&m=131983853831049&w=2) forgot to
remove the ARM specific definition of 'pcibios_max_latency' once such
had been moved into the pci core resulting in ARM related compile
errors -
drivers/built-in.o:(.data+0x230): multiple definition of
`pcibios_max_latency'
arch/arm/common/built-in.o:(.data+0x40c): first defined here
make[1]: *** [vmlinux.o] Error 1
In the series, patch 2/16 (commit 168c8619fd8) converted the ARM
specific version of 'pcibios_set_master()' to a non-inlined version.
This was done in preperation for hosting it up into PCI's core, which
was done in patch 10/16 (commit 96c5590058d) of the series (and
where the removal of ARM's 'pcibios_max_latency' was overlooked).
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Myron Stowe <myron.stowe@redhat.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/common/it8152.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index d1bcd7b13ebc..fb1f1cfce60c 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c @@ -320,13 +320,6 @@ err0: return -EBUSY; } -/* - * If we set up a device for bus mastering, we need to check the latency - * timer as we don't have even crappy BIOSes to set it properly. - * The implementation is from arch/i386/pci/i386.c - */ -unsigned int pcibios_max_latency = 255; - /* ITE bridge requires setting latency timer to avoid early bus access termination by PCI bus master devices */ |