Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux

Pull clk framework fixes from Mike Turquette:
 "Clock framework and driver fixes, all of which fix user-visible
  regressions.

  There is a single framework fix that prevents dereferencing a NULL
  pointer when calling clk_get.  The range of fixes for clock driver
  regressions spans memory leak fixes, touching the wrong registers that
  cause things to explode, misconfigured clock rates that result in
  non-responsive devices and even some boot failures.  The most benign
  fix is DT binding doc typo.  It is a stable ABI exposed from the
  kernel that was introduced in -rc1, so best to fix it now"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
  clk:at91: Fix memory leak in of_at91_clk_master_setup()
  clk: nomadik: fix multiplatform problem
  clk: Correct handling of NULL clk in __clk_{get, put}
  clk: shmobile: Fix typo in MSTP clock DT bindings
  clk: shmobile: rcar-gen2: Fix qspi divisor
  clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocks
  clk: tegra124: remove gr2d and gr3d clocks
  clk: tegra: Fix vic03 mux index
  clk: shmobile: rcar-gen2: Fix qspi divisor
  clk: shmobile: rcar-gen2: Fix clock parent all non-PLL clocks
  clk: tegra: use max divider if divider overflows
  clk: tegra: cclk_lp has a pllx/2 divider
  clk: tegra: fix sdmmc clks on Tegra1x4
  clk: tegra: fix host1x clock on Tegra124
  clk: tegra: PLLD2 fixes for hdmi
  clk: tegra: Fix PLLD mnp table
  clk: tegra: Fix PLLP rate table
  clk: tegra: Correct clock number for UARTE
  clk: tegra: Add missing Tegra20 fuse clks
  ARM: keystone: dts: fix clkvcp3 control register address
  ...

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index 2363593e1050..ef58d1c24313 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -612,7 +612,7 @@ clocks {
 		compatible = "ti,keystone,psc-clock";
 		clocks = <&chipclk13>;
 		clock-output-names = "vcp-3";
-		reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
+		reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
 		reg-names = "control", "domain";
 		domain-id = <24>;
 	};