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authorLinus Walleij <linus.walleij@linaro.org>2015-07-30 15:19:25 +0200
committerMichael Turquette <mturquette@baylibre.com>2015-08-24 16:49:14 -0700
commit5dc0fe199b358966021b015c71ca4049d0f42aa6 (patch)
tree6535c2dbda550a6a5d1353fd96dba05d6eec98dd /arch/arm
parentc660b2ebb25be5668a4ed333539f34b05841e17a (diff)
downloadlinux-5dc0fe199b358966021b015c71ca4049d0f42aa6.tar.bz2
clk/ARM: move Ux500 PRCC bases to the device tree
The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi7
-rw-r--r--arch/arm/mach-ux500/cpu.c21
2 files changed, 13 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 853684ad7773..a56bf890afaf 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -219,6 +219,13 @@
clocks {
compatible = "stericsson,u8500-clks";
+ /*
+ * Registers for the CLKRST block on peripheral
+ * groups 1, 2, 3, 5, 6,
+ */
+ reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
+ <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
+ <0xa03cf000 0x1000>;
prcmu_clk: prcmu-clock {
#clock-cells = <1>;
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e31d3d61c998..b316e18a76aa 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -72,21 +72,12 @@ void __init ux500_init_irq(void)
* Init clocks here so that they are available for system timer
* initialization.
*/
- if (cpu_is_u8500_family()) {
- u8500_of_clk_init(U8500_CLKRST1_BASE,
- U8500_CLKRST2_BASE,
- U8500_CLKRST3_BASE,
- U8500_CLKRST5_BASE,
- U8500_CLKRST6_BASE);
- } else if (cpu_is_u9540()) {
- u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
- U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
- U8500_CLKRST6_BASE);
- } else if (cpu_is_u8540()) {
- u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
- U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
- U8500_CLKRST6_BASE);
- }
+ if (cpu_is_u8500_family())
+ u8500_clk_init();
+ else if (cpu_is_u9540())
+ u9540_clk_init();
+ else if (cpu_is_u8540())
+ u8540_clk_init();
}
static const char * __init ux500_get_machine(void)