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| author | Arnd Bergmann <arnd@arndb.de> | 2021-10-05 15:33:31 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2021-10-05 15:33:32 +0200 |
| commit | c147392b652b6af7d96f1f844a4938a6bb4921b8 (patch) | |
| tree | eb60974f880cfce7afe4f2b7becd05017ef15d0b /arch/arm | |
| parent | 325c81e3fd52cb4dce1f5e7cc789bc82f2772ab2 (diff) | |
| parent | ecf5b34cd5182180ff47ca14ecaca0a90db7fd1d (diff) | |
| download | linux-c147392b652b6af7d96f1f844a4938a6bb4921b8.tar.bz2 | |
Merge tag 'qcom-dts-fixes-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
Qualcomm DTS fixes for v5.15
This corrects the use of depricated chipid and clock names, for which
support was finally dropped from the driver. It also ensures that the
DSI PLL is fed by the correct clock, now that it's being migrated to not
rely on global clock names.
* tag 'qcom-dts-fixes-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: apq8064: update Adreno clock names
ARM: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL reference
ARM: dts: qcom: apq8064: use compatible which contains chipid
Link: https://lore.kernel.org/r/20210930025526.1146-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8064.dtsi | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 0b2bed6e7adf..d1c1c6aab2b8 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -198,7 +198,7 @@ clock-frequency = <19200000>; }; - pxo_board { + pxo_board: pxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; @@ -1148,22 +1148,21 @@ }; gpu: adreno-3xx@4300000 { - compatible = "qcom,adreno-3xx"; + compatible = "qcom,adreno-320.2", "qcom,adreno"; reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "kgsl_3d0_irq"; clock-names = - "core_clk", - "iface_clk", - "mem_clk", - "mem_iface_clk"; + "core", + "iface", + "mem", + "mem_iface"; clocks = <&mmcc GFX3D_CLK>, <&mmcc GFX3D_AHB_CLK>, <&mmcc GFX3D_AXI_CLK>, <&mmcc MMSS_IMEM_AHB_CLK>; - qcom,chipid = <0x03020002>; iommus = <&gfx3d 0 &gfx3d 1 @@ -1306,7 +1305,7 @@ reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; clock-names = "iface_clk", "ref"; clocks = <&mmcc DSI_M_AHB_CLK>, - <&cxo_board>; + <&pxo_board>; }; |