diff options
| author | Viresh Kumar <viresh.kumar@linaro.org> | 2018-05-25 16:02:00 +0530 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-07-21 16:18:14 -0500 |
| commit | b0c28f2765813e816740028dd85e64e46eee15a0 (patch) | |
| tree | eb583d5fd00dd12e1f9c18611e57f3f7007f3b14 /arch/arm | |
| parent | 03864e57770a9541e7ff3990bacf2d9a2fffcd5d (diff) | |
| download | linux-b0c28f2765813e816740028dd85e64e46eee15a0.tar.bz2 | |
ARM: dts: qcom: Add missing OPP properties for CPUs
The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing property (clock latency) as well to make it all
work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 7bcd7635e723..78db67337ed4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -77,6 +77,14 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@2 { @@ -88,6 +96,14 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; cpu@3 { @@ -99,6 +115,14 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; }; }; |