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authorTony Lindgren <tony@atomide.com>2019-01-29 07:53:47 -0800
committerTony Lindgren <tony@atomide.com>2019-01-29 07:53:47 -0800
commit072167d13ce46d5fcef1a80a53a667a46c9b17e7 (patch)
treed978e8c7d523702d8da2964c02a10f3301015847 /arch/arm
parentd0243693fbf6fbd48b4efb2ba7210765983b03e3 (diff)
parent0840242e887586268f665bf58d5e1a7d6ebf35ed (diff)
downloadlinux-072167d13ce46d5fcef1a80a53a667a46c9b17e7.tar.bz2
Merge branch 'pwm-dmtimer-fixes' into omap-for-v5.0/fixes-v2
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/omap4-droid4-xt894.dts11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index 04758a2a87f0..67d77eee9433 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -644,6 +644,17 @@
};
};
+/* Configure pwm clock source for timers 8 & 9 */
+&timer8 {
+ assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+};
+
+&timer9 {
+ assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+};
+
/*
* As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
* uart1 wakeirq.