Merge branch 'for-next/perf' into for-next/core

PMU driver cleanups for managing IRQ affinity and exposing event
attributes via sysfs.

* for-next/perf: (36 commits)
  drivers/perf: fix the missed ida_simple_remove() in ddr_perf_probe()
  perf/arm-cmn: Fix invalid pointer when access dtc object sharing the same IRQ number
  arm64: perf: Simplify EVENT ATTR macro in perf_event.c
  drivers/perf: Simplify EVENT ATTR macro in fsl_imx8_ddr_perf.c
  drivers/perf: Simplify EVENT ATTR macro in xgene_pmu.c
  drivers/perf: Simplify EVENT ATTR macro in qcom_l3_pmu.c
  drivers/perf: Simplify EVENT ATTR macro in qcom_l2_pmu.c
  drivers/perf: Simplify EVENT ATTR macro in SMMU PMU driver
  perf: Add EVENT_ATTR_ID to simplify event attributes
  perf/smmuv3: Don't trample existing events with global filter
  perf/hisi: Constify static attribute_group structs
  perf: qcom: Remove redundant dev_err call in qcom_l3_cache_pmu_probe()
  drivers/perf: hisi: Fix data source control
  arm64: perf: Add more support on caps under sysfs
  perf: qcom_l2_pmu: move to use request_irq by IRQF_NO_AUTOEN flag
  arm_pmu: move to use request_irq by IRQF_NO_AUTOEN flag
  perf: arm_spe: use DEVICE_ATTR_RO macro
  perf: xgene_pmu: use DEVICE_ATTR_RO macro
  perf: qcom: use DEVICE_ATTR_RO macro
  perf: arm_pmu: use DEVICE_ATTR_RO macro
  ...

1 files changed, 35 insertions, 5 deletions

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index f594957e29bd..d07788dad388 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -165,10 +165,7 @@ armv8pmu_events_sysfs_show(struct device *dev,
 }
 
 #define ARMV8_EVENT_ATTR(name, config)						\
-	(&((struct perf_pmu_events_attr) {					\
-		.attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL),	\
-		.id = config,							\
-	}).attr.attr)
+	PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
 
 static struct attribute *armv8_pmuv3_event_attrs[] = {
 	ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
@@ -312,13 +309,46 @@ static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
 	struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 	u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
 
-	return snprintf(page, PAGE_SIZE, "0x%08x\n", slots);
+	return sysfs_emit(page, "0x%08x\n", slots);
 }
 
 static DEVICE_ATTR_RO(slots);
 
+static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
+			      char *page)
+{
+	struct pmu *pmu = dev_get_drvdata(dev);
+	struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
+	u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
+			& ARMV8_PMU_BUS_SLOTS_MASK;
+
+	return sysfs_emit(page, "0x%08x\n", bus_slots);
+}
+
+static DEVICE_ATTR_RO(bus_slots);
+
+static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
+			      char *page)
+{
+	struct pmu *pmu = dev_get_drvdata(dev);
+	struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
+	u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
+			& ARMV8_PMU_BUS_WIDTH_MASK;
+	u32 val = 0;
+
+	/* Encoded as Log2(number of bytes), plus one */
+	if (bus_width > 2 && bus_width < 13)
+		val = 1 << (bus_width - 1);
+
+	return sysfs_emit(page, "0x%08x\n", val);
+}
+
+static DEVICE_ATTR_RO(bus_width);
+
 static struct attribute *armv8_pmuv3_caps_attrs[] = {
 	&dev_attr_slots.attr,
+	&dev_attr_bus_slots.attr,
+	&dev_attr_bus_width.attr,
 	NULL,
 };