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| author | Marc Zyngier <marc.zyngier@arm.com> | 2015-11-16 10:28:18 +0000 |
|---|---|---|
| committer | Christoffer Dall <christoffer.dall@linaro.org> | 2015-11-24 17:58:14 +0100 |
| commit | 498cd5c32be6e32bc0f8efcad48ab094bb2bfdf3 (patch) | |
| tree | a82a2907c46684fcb8d15909de334dc48459a22e /arch/arm64/include | |
| parent | c0f0963464c24e034b858441205455bf2a5d93ad (diff) | |
| download | linux-498cd5c32be6e32bc0f8efcad48ab094bb2bfdf3.tar.bz2 | |
arm64: KVM: Add workaround for Cortex-A57 erratum 834220
Cortex-A57 parts up to r1p2 can misreport Stage 2 translation faults
when a Stage 1 permission fault or device alignment fault should
have been reported.
This patch implements the workaround (which is to validate that the
Stage-1 translation actually succeeds) by using code patching.
Cc: stable@vger.kernel.org
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/cpufeature.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 11d5bb0fdd54..52722ee73dba 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -29,8 +29,9 @@ #define ARM64_HAS_PAN 4 #define ARM64_HAS_LSE_ATOMICS 5 #define ARM64_WORKAROUND_CAVIUM_23154 6 +#define ARM64_WORKAROUND_834220 7 -#define ARM64_NCAPS 7 +#define ARM64_NCAPS 8 #ifndef __ASSEMBLY__ |