diff options
| author | Mark Brown <broonie@kernel.org> | 2022-05-10 17:11:59 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-05-16 19:50:20 +0100 |
| commit | a6dab6cc0f4cd0b341f002ce7d0683701612f527 (patch) | |
| tree | 07bf59d6c258ef605df16d48fee27438065e93d9 /arch/arm64/include | |
| parent | 5b06dcfd9e0a5dd63ecadf9169ee92a80b063322 (diff) | |
| download | linux-a6dab6cc0f4cd0b341f002ce7d0683701612f527.tar.bz2 | |
arm64/sme: Drop SYS_ from SMIDR_EL1 defines
We currently have a non-standard SYS_ prefix in the constants generated
for SMIDR_EL1 bitfields. Drop this in preparation for automatic register
definition generation, no functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220510161208.631259-4-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/el2_setup.h | 2 | ||||
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index fabdbde0fe02..34ceff08cac4 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -171,7 +171,7 @@ msr_s SYS_SMCR_EL2, x1 // length for EL1. mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? - ubfx x1, x1, #SYS_SMIDR_EL1_SMPS_SHIFT, #1 + ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 cbz x1, .Lskip_sme_\@ msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b83808ebc58f..ab2d7cbc63fc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -467,9 +467,9 @@ #define SYS_SMIDR_EL1 sys_reg(3, 1, 0, 0, 6) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) -#define SYS_SMIDR_EL1_IMPLEMENTER_SHIFT 24 -#define SYS_SMIDR_EL1_SMPS_SHIFT 15 -#define SYS_SMIDR_EL1_AFFINITY_SHIFT 0 +#define SMIDR_EL1_IMPLEMENTER_SHIFT 24 +#define SMIDR_EL1_SMPS_SHIFT 15 +#define SMIDR_EL1_AFFINITY_SHIFT 0 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) |