diff options
| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2017-03-14 18:13:27 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-03-20 16:30:22 +0000 |
| commit | c651aae5a7732287c1c9bc974ece4ed798780544 (patch) | |
| tree | bc3647b41e405e93747c80021850563d6a49d7db /arch/arm64/include/asm/sysreg.h | |
| parent | cb567e79fa504575cb97fb2f866d2040ed1c92e7 (diff) | |
| download | linux-c651aae5a7732287c1c9bc974ece4ed798780544.tar.bz2 | |
arm64: v8.3: Support for weaker release consistency
ARMv8.3 adds new instructions to support Release Consistent
processor consistent (RCpc) model, which is weaker than the
RCsc model.
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 69af995c9b76..c776bde940bd 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -157,6 +157,7 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64isar1 */ +#define ID_AA64ISAR1_LRCPC_SHIFT 20 #define ID_AA64ISAR1_FCMA_SHIFT 16 #define ID_AA64ISAR1_JSCVT_SHIFT 12 |