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| author | Julien Thierry <julien.thierry@arm.com> | 2019-01-31 14:58:46 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2019-02-06 10:05:18 +0000 |
| commit | 133d05186325ce04494ea6488a6b86e50a446c12 (patch) | |
| tree | 3d9b43fc48c46a1d94978aa6e20dfaae32920cdc /arch/arm64/include/asm/processor.h | |
| parent | cdbc81ddef43c8fdcbd3a26e1a7530c70b629cfc (diff) | |
| download | linux-133d05186325ce04494ea6488a6b86e50a446c12.tar.bz2 | |
arm64: Make PMR part of task context
In order to replace PSR.I interrupt disabling/enabling with ICC_PMR_EL1
interrupt masking, ICC_PMR_EL1 needs to be saved/restored when
taking/returning from an exception. This mimics the way hardware saves
and restores PSR.I bit in spsr_el1 for exceptions and ERET.
Add PMR to the registers to save in the pt_regs struct upon kernel entry,
and restore it before ERET. Also, initialize it to a sane value when
creating new tasks.
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/processor.h')
| -rw-r--r-- | arch/arm64/include/asm/processor.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index f1a7ab18faf3..5d9ce62bdebd 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -191,6 +191,9 @@ static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) memset(regs, 0, sizeof(*regs)); forget_syscall(regs); regs->pc = pc; + + if (system_uses_irq_prio_masking()) + regs->pmr_save = GIC_PRIO_IRQON; } static inline void start_thread(struct pt_regs *regs, unsigned long pc, |