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authorWill Deacon <will@kernel.org>2022-03-14 19:04:22 +0000
committerWill Deacon <will@kernel.org>2022-03-14 19:04:22 +0000
commit8d93b7a242b2adf36949c10b8eb9cc084a74b59a (patch)
treedc6a45f281eb89c5b35ceef5698400b9ee11b237 /arch/arm64/include/asm/cpufeature.h
parent515e5da7b6b52c5d6c7a54fe34165b86361041b5 (diff)
parentf2c281204b47309534f26dc63cee2a130c2b497b (diff)
downloadlinux-8d93b7a242b2adf36949c10b8eb9cc084a74b59a.tar.bz2
Merge branch 'for-next/fpsimd' into for-next/core
* for-next/fpsimd: arm64: cpufeature: Warn if we attempt to read a zero width field arm64: cpufeature: Add missing .field_width for GIC system registers arm64: signal: nofpsimd: Do not allocate fp/simd context when not available arm64: cpufeature: Always specify and use a field width for capabilities arm64: Always use individual bits in CPACR floating point enables arm64: Define CPACR_EL1_FPEN similarly to other floating point controls
Diffstat (limited to 'arch/arm64/include/asm/cpufeature.h')
-rw-r--r--arch/arm64/include/asm/cpufeature.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index fe7137ff6190..380238ae3321 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -356,6 +356,7 @@ struct arm64_cpu_capabilities {
struct { /* Feature register checking */
u32 sys_reg;
u8 field_pos;
+ u8 field_width;
u8 min_field_value;
u8 hwcap_type;
bool sign;
@@ -576,6 +577,8 @@ static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
static inline int __attribute_const__
cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
{
+ if (WARN_ON_ONCE(!width))
+ width = 4;
return (sign) ?
cpuid_feature_extract_signed_field_width(features, field, width) :
cpuid_feature_extract_unsigned_field_width(features, field, width);