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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-08-27 13:02:43 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-09-10 16:10:09 +0100 |
| commit | 86d0dd34eafffbc76a81aba6ae2d71927d3835a8 (patch) | |
| tree | b083d6e8636d919c268a8b6fef9d0311e77f50dd /arch/arm64/include/asm/cpucaps.h | |
| parent | 9784d82db3eb3de7851e5a3f4a2481607de2452c (diff) | |
| download | linux-86d0dd34eafffbc76a81aba6ae2d71927d3835a8.tar.bz2 | |
arm64: cpufeature: add feature for CRC32 instructions
Add a CRC32 feature bit and wire it up to the CPU id register so we
will be able to use alternatives patching for CRC32 operations.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index ae1f70450fb2..9932aca9704b 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -51,7 +51,8 @@ #define ARM64_SSBD 30 #define ARM64_MISMATCHED_CACHE_TYPE 31 #define ARM64_HAS_STAGE2_FWB 32 +#define ARM64_HAS_CRC32 33 -#define ARM64_NCAPS 33 +#define ARM64_NCAPS 34 #endif /* __ASM_CPUCAPS_H */ |