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authorShawn Guo <shawn.guo@linaro.org>2017-03-21 16:42:45 +0800
committerShawn Guo <shawnguo@kernel.org>2017-03-24 16:16:50 +0800
commit6d7e05ab8ff6f6bb91ecfbbd542240c7b6c23502 (patch)
treedbe88d8abdc7473b3e3b99cfde2389c6a8ee67ae /arch/arm64/boot/dts/zte
parentc1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201 (diff)
downloadlinux-6d7e05ab8ff6f6bb91ecfbbd542240c7b6c23502.tar.bz2
arm64: dts: zte: remove zx296718 pll_vga clock
Rather than a fixed rate clock, pll_vga is a PLL can be programmed into different freqencies. Let's drop it from device tree and get it registered from clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/zte')
-rw-r--r--arch/arm64/boot/dts/zte/zx296718.dtsi7
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi
index b850b2cd0adc..1f256495b902 100644
--- a/arch/arm64/boot/dts/zte/zx296718.dtsi
+++ b/arch/arm64/boot/dts/zte/zx296718.dtsi
@@ -235,13 +235,6 @@
clock-output-names = "pll_mac";
};
- pll_vga: clk-pll-1073m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1073000000>;
- clock-output-names = "pll_vga";
- };
-
pll_mm0: clk-pll-1188m {
compatible = "fixed-clock";
#clock-cells = <0>;