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| author | Rajendra Nayak <rnayak@codeaurora.org> | 2020-09-01 19:50:26 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-09-10 22:03:16 +0000 |
| commit | ef8e58f837e6f5659ca8dc2c49dfe3eaf17a02e1 (patch) | |
| tree | 900e1f1d448d5c6c8ea04eaafd46b5d77959cfd6 /arch/arm64/boot/dts/qcom/sc7180.dtsi | |
| parent | 137154871cf469af0e8def123511c37096583919 (diff) | |
| download | linux-ef8e58f837e6f5659ca8dc2c49dfe3eaf17a02e1.tar.bz2 | |
arm64: dts: qcom: sc7180: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state
of a power-domain
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7180.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 90debb4e4c11..0a80a5ccbe50 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2705,8 +2705,10 @@ reg = <0 0x0aa00000 0 0xff000>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&videocc VENUS_GDSC>, - <&videocc VCODEC0_GDSC>; - power-domain-names = "venus", "vcodec0"; + <&videocc VCODEC0_GDSC>, + <&rpmhpd SC7180_CX>; + power-domain-names = "venus", "vcodec0", "cx"; + operating-points-v2 = <&venus_opp_table>; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, @@ -2727,6 +2729,35 @@ video-encoder { compatible = "venus-encoder"; }; + + venus_opp_table: venus-opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-434000000 { + opp-hz = /bits/ 64 <434000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-500000097 { + opp-hz = /bits/ 64 <500000097>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; }; videocc: clock-controller@ab00000 { |