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| author | David S. Miller <davem@davemloft.net> | 2006-02-23 14:19:28 -0800 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2006-03-20 01:14:00 -0800 |
| commit | a0663a79ad4faebe1db4a56e2e767b120b12333a (patch) | |
| tree | 612a53e387a6aea6116f8a1637050fa13c6d9f80 /arch/arm26 | |
| parent | 074d82cf688fe2dfa7ba4a2317c56f62d13fb522 (diff) | |
| download | linux-a0663a79ad4faebe1db4a56e2e767b120b12333a.tar.bz2 | |
[SPARC64]: Fix TLB context allocation with SMT style shared TLBs.
The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness. Chips like Niagara
break this assumption.
So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.
Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm26')
0 files changed, 0 insertions, 0 deletions