diff options
| author | Seungwhan Youn <sw.youn@samsung.com> | 2010-10-14 10:39:08 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-25 16:05:56 +0900 |
| commit | d4b34c6c849d67b7afaa90d55dc7fab981c72950 (patch) | |
| tree | c6b5c6bfe622832865a98fecec1159cb350bc18a /arch/arm/plat-s5p/clock.c | |
| parent | 900fa0196c564895bfa2eb412d2a83421d3f3444 (diff) | |
| download | linux-d4b34c6c849d67b7afaa90d55dc7fab981c72950.tar.bz2 | |
ARM: S5P: Reduce duplicated EPLL control codes
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other
H/W blocks. Until now, to control EPLL, each of SoCs make their own functions
in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and
'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move
these duplicated codes to common EPLL functions that use platform wide.
Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
Acked-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-s5p/clock.c')
| -rw-r--r-- | arch/arm/plat-s5p/clock.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index 818800962694..8d081d968c58 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c @@ -21,6 +21,8 @@ #include <linux/io.h> #include <asm/div64.h> +#include <mach/regs-clock.h> + #include <plat/clock.h> #include <plat/clock-clksrc.h> #include <plat/s5p-clock.h> @@ -148,6 +150,24 @@ int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) return 0; } +int s5p_epll_enable(struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; + + if (enable) + __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); + else + __raw_writel(epll_con, S5P_EPLL_CON); + + return 0; +} + +unsigned long s5p_epll_get_rate(struct clk *clk) +{ + return clk->rate; +} + static struct clk *s5p_clks[] __initdata = { &clk_ext_xtal_mux, &clk_48m, |