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author | Paul Walmsley <paul@pwsan.com> | 2009-06-19 19:08:27 -0600 |
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committer | paul <paul@twilight.(none)> | 2009-06-19 19:09:31 -0600 |
commit | d0ba3922ae241a87d22a1c3ffad72b96fe993c9a (patch) | |
tree | 3f23d60fbbf2ffceef44b01c8579db7be7d20025 /arch/arm/plat-omap/sram.c | |
parent | c9812d042a21eb492a36cfabf9f41107f5ecee3d (diff) | |
download | linux-d0ba3922ae241a87d22a1c3ffad72b96fe993c9a.tar.bz2 |
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change
Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency. Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/plat-omap/sram.c')
-rw-r--r-- | arch/arm/plat-omap/sram.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 79c0f0254426..7dadf1a59fb5 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -372,16 +372,16 @@ static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f); + u32 f, u32 sdrc_mr); u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll, - u32 f) + u32 f, u32 sdrc_mr) { BUG_ON(!_omap3_sram_configure_core_dpll); return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, sdrc_actim_ctrla, sdrc_actim_ctrlb, m2, - unlock_dll, f); + unlock_dll, f, sdrc_mr); } /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ |