diff options
author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-12 11:10:55 +0100 |
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committer | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2010-11-19 21:54:35 +0100 |
commit | 6a697e3d310d79ea0e385975c57084ce22b04b36 (patch) | |
tree | 64462dc21a24ad331214e834abd30eede199d0c5 /arch/arm/plat-mxc/include/mach/mx31.h | |
parent | a528bc87841d958bbd394abc9266aee9cdf45cb8 (diff) | |
download | linux-6a697e3d310d79ea0e385975c57084ce22b04b36.tar.bz2 |
ARM: mx3: dynamically register mxc-mmc devices
Compared to the static devices the dynamic have a DMA resource.
This should be save as it seems unused in the driver.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mx31.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 6d4b98f48f4b..d024c9c5dd3f 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -41,8 +41,8 @@ #define MX31_SPBA0_BASE_ADDR 0x50000000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) @@ -134,8 +134,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_MPEG4_ENCODER 5 #define MX31_INT_RTIC 6 #define MX31_INT_FIRI 7 -#define MX31_INT_MMC_SDHC2 8 -#define MX31_INT_MMC_SDHC1 9 +#define MX31_INT_SDHC2 8 +#define MX31_INT_SDHC1 9 #define MX31_INT_I2C1 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 @@ -188,6 +188,8 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define MX31_DMA_REQ_SDHC1 20 +#define MX31_DMA_REQ_SDHC2 21 #define MX31_DMA_REQ_SSI2_RX1 22 #define MX31_DMA_REQ_SSI2_TX1 23 #define MX31_DMA_REQ_SSI2_RX0 24 |