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| author | Catalin Marinas <catalin.marinas@arm.com> | 2007-02-05 14:47:40 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-08 14:49:24 +0000 |
| commit | 9d99df4b10eef130dacb5f772cd589c625b03634 (patch) | |
| tree | bf1cea618ef9380cdce9cfea8897da9fb961787b /arch/arm/mm/tlb-v6.S | |
| parent | 620879c9e33262426db0ade650be5d7a2046377b (diff) | |
| download | linux-9d99df4b10eef130dacb5f772cd589c625b03634.tar.bz2 | |
[ARM] 4128/1: Architecture compliant TTBR changing sequence
On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/tlb-v6.S')
0 files changed, 0 insertions, 0 deletions