diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-04-07 13:17:15 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-04-07 13:23:57 +0100 |
| commit | 95f3df6bcb89d370c57b7165f55c5a409d011c8e (patch) | |
| tree | 9accc55603a6274a281fce6950fbef26f051a2c5 /arch/arm/mm/proc-sa1100.S | |
| parent | f1dc24d53e9e91cf795f05751eeb7e220c7c15e1 (diff) | |
| download | linux-95f3df6bcb89d370c57b7165f55c5a409d011c8e.tar.bz2 | |
[ARM] Fix SA110/SA1100 cache flushing
We had two implementations for flushing the cache, which meant StrongARM
caches weren't being correctly flushed. Fix this by always using the
v4wb_flush_kern_cache_all method, rather than duplicating it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-sa1100.S')
| -rw-r--r-- | arch/arm/mm/proc-sa1100.S | 37 |
1 files changed, 5 insertions, 32 deletions
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 41f21f2dd8ff..777ad99c1439 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -30,30 +30,6 @@ * the cache line size of the I and D cache */ #define DCACHELINESIZE 32 -#define FLUSH_OFFSET 32768 - - .macro flush_1100_dcache rd, ra, re - ldr \rd, =flush_base - ldr \ra, [\rd] - eor \ra, \ra, #FLUSH_OFFSET - str \ra, [\rd] - add \re, \ra, #8192 @ only necessary for 8k -1001: ldr \rd, [\ra], #DCACHELINESIZE - teq \re, \ra - bne 1001b -#ifdef FLUSH_BASE_MINICACHE - add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE - add \re, \ra, #512 @ only 512 bytes -1002: ldr \rd, [\ra], #DCACHELINESIZE - teq \re, \ra - bne 1002b -#endif - .endm - - .data -flush_base: - .long FLUSH_BASE - .text __INIT @@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin) stmfd sp!, {lr} mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE msr cpsr_c, ip - flush_1100_dcache r0, r1, r2 @ clean caches - mov r0, #0 - mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching + bl v4wb_flush_kern_cache_all + mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching mrc p15, 0, r0, c1, c0, 0 @ ctrl register bic r0, r0, #0x1000 @ ...i............ bic r0, r0, #0x000e @ ............wca. @@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area) */ .align 5 ENTRY(cpu_sa1100_switch_mm) - flush_1100_dcache r3, ip, r1 - mov ip, #0 - mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache + str lr, [sp, #-4]! + bl v4wb_flush_kern_cache_all @ clears IP mcr p15, 0, ip, c9, c0, 0 @ invalidate RB - mcr p15, 0, ip, c7, c10, 4 @ drain WB mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs - mov pc, lr + ldr pc, [sp], #4 /* * cpu_sa1100_set_pte(ptep, pte) |