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| author | Rabin Vincent <rabinv@axis.com> | 2016-11-08 09:21:19 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-01-10 23:31:30 +0000 |
| commit | 00a19f3e25c0c40e0ec77f52d4841d23ad269169 (patch) | |
| tree | 3371f5f7e4a0298833e1d5186aa5e9cb07937c10 /arch/arm/mm/flush.c | |
| parent | 7ce7d89f48834cefece7804d38fc5d85382edf77 (diff) | |
| download | linux-00a19f3e25c0c40e0ec77f52d4841d23ad269169.tar.bz2 | |
ARM: 8627/1: avoid cache flushing in flush_dcache_page()
When the data cache is PIPT or VIPT non-aliasing, and cache operations
are broadcast by the hardware, we can always postpone the flush in
flush_dcache_page(). A similar change was done for ARM64 in commit
b5b6c9e9149d ("arm64: Avoid cache flushing in flush_dcache_page()").
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/flush.c')
| -rw-r--r-- | arch/arm/mm/flush.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 3cced8455727..f1e6190aa7ea 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -327,6 +327,12 @@ void flush_dcache_page(struct page *page) if (page == ZERO_PAGE(0)) return; + if (!cache_ops_need_broadcast() && cache_is_vipt_nonaliasing()) { + if (test_bit(PG_dcache_clean, &page->flags)) + clear_bit(PG_dcache_clean, &page->flags); + return; + } + mapping = page_mapping(page); if (!cache_ops_need_broadcast() && |