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authorSoren Brinkmann <soren.brinkmann@xilinx.com>2012-12-19 10:18:39 -0800
committerMichal Simek <michal.simek@xilinx.com>2013-01-28 13:27:24 +0100
commitd16aaf47ee2e668cc68a881bb957f0a7273d30ab (patch)
treeedd3bf010dd77867279d45ab930c8649e1650c3d /arch/arm/mach-zynq
parentec5b849ed77cd583fd888dfb41b6ebeb3989ec1a (diff)
downloadlinux-d16aaf47ee2e668cc68a881bb957f0a7273d30ab.tar.bz2
arm: zynq: timer: Align columns
Aligning the columns in a block of #defines, so that the values are starting in the same colum on every line. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Diffstat (limited to 'arch/arm/mach-zynq')
-rw-r--r--arch/arm/mach-zynq/timer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 80bf4742fe37..4b81ae1153d3 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -35,9 +35,9 @@
* Timer Register Offset Definitions of Timer 1, Increment base address by 4
* and use same offsets for Timer 2
*/
-#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
+#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
+#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
+#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */