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author | Arnd Bergmann <arnd@arndb.de> | 2013-05-06 23:43:45 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2013-05-06 23:43:45 +0200 |
commit | 442a33ebce9e02a2dd6662f16c9f2aad834d0115 (patch) | |
tree | ca8654a286f61da917318645cab9e061095ecdba /arch/arm/mach-versatile/core.c | |
parent | a94d236dc355f374857ee4e6e78b7dec8a0f29e3 (diff) | |
parent | f31c2f1c68aff83277eddc6798adf3438e9c680a (diff) | |
download | linux-442a33ebce9e02a2dd6662f16c9f2aad834d0115.tar.bz2 |
Merge branch 'late/clksrc' into late/cleanup
There is no reason to keep the clksrc cleanups separate from the
other cleanups, and this resolves some merge conflicts.
Conflicts:
arch/arm/mach-spear/spear13xx.c
drivers/irqchip/Makefile
Diffstat (limited to 'arch/arm/mach-versatile/core.c')
-rw-r--r-- | arch/arm/mach-versatile/core.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 25160aeaa3b7..54bb80b012ac 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -749,12 +749,25 @@ void versatile_restart(char mode, const char *cmd) /* Early initializations */ void __init versatile_init_early(void) { + u32 val; void __iomem *sys = __io_address(VERSATILE_SYS_BASE); osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET; clkdev_add_table(lookups, ARRAY_SIZE(lookups)); versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000); + + /* + * set clock frequency: + * VERSATILE_REFCLK is 32KHz + * VERSATILE_TIMCLK is 1MHz + */ + val = readl(__io_address(VERSATILE_SCTL_BASE)); + writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | + (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, + __io_address(VERSATILE_SCTL_BASE)); } void __init versatile_init(void) @@ -785,19 +798,6 @@ void __init versatile_init(void) */ void __init versatile_timer_init(void) { - u32 val; - - /* - * set clock frequency: - * VERSATILE_REFCLK is 32KHz - * VERSATILE_TIMCLK is 1MHz - */ - val = readl(__io_address(VERSATILE_SCTL_BASE)); - writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | - (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val, - __io_address(VERSATILE_SCTL_BASE)); /* * Initialise to a known state (all timers off) |