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| author | Joseph Lo <josephl@nvidia.com> | 2013-07-03 17:50:37 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-07-19 10:08:04 -0600 |
| commit | c04c77540a4f996ee94d0240bbae3a7512febd37 (patch) | |
| tree | a480639fb642cb10b9bf738f294f68ed40e99b5c /arch/arm/mach-tegra/headsmp.S | |
| parent | 3045cb33eb6081a937d9a2873f5fb88d9fcb7900 (diff) | |
| download | linux-c04c77540a4f996ee94d0240bbae3a7512febd37.tar.bz2 | |
ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9
The v7_invalidate_l1 was used for the L1 cache that come out from reset
in a undefined state. This is no need for Cortex-A15. We do it for A9
only.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 045c16f2dd51..2072e7322c39 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -6,6 +6,7 @@ .section ".text.head", "ax" ENTRY(tegra_secondary_startup) - bl v7_invalidate_l1 + check_cpu_part_num 0xc09, r8, r9 + bleq v7_invalidate_l1 b secondary_startup ENDPROC(tegra_secondary_startup) |