diff options
| author | Stephen Warren <swarren@nvidia.com> | 2012-04-12 14:13:05 -0600 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-04-25 15:22:09 -0600 |
| commit | 9abafa021e223f04d6589ee2b977bbaf2e1f1367 (patch) | |
| tree | 6029d68e9dc837b40677282e459fc807aa76e581 /arch/arm/mach-tegra/board-paz00.c | |
| parent | 7ff4db0967bd7d617c77dc5a66c0d95166277817 (diff) | |
| download | linux-9abafa021e223f04d6589ee2b977bbaf2e1f1367.tar.bz2 | |
ARM: tegra: change pll_p_out4's rate to 24MHz
pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.
Remove board-paz00.c's now-duplicate initialization of this clock.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-paz00.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-paz00.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 330afdfa2475..aebfa4003813 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -176,7 +176,6 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { { "uarta", "pll_p", 216000000, true }, { "uartc", "pll_p", 216000000, true }, - { "pll_p_out4", "pll_p", 24000000, true }, { "usbd", "clk_m", 12000000, false }, { "usb2", "clk_m", 12000000, false }, { "usb3", "clk_m", 12000000, false }, |