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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-20 11:23:13 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-20 15:44:43 -0500 |
| commit | cd871d517d46f26943f3c8f61c0d2ac6665da6a2 (patch) | |
| tree | 5abb55bbf4bb30df7694d27a4e783c4a4e5aadd1 /arch/arm/mach-socfpga/core.h | |
| parent | b33612e183dcbaa2cc2479cedff6984a6cccdf6a (diff) | |
| download | linux-cd871d517d46f26943f3c8f61c0d2ac6665da6a2.tar.bz2 | |
ARM: socfpga: add reset for the Arria 10 platform
Since the Arria10's reset register offset is different from the Cyclone/Arria 5,
it's best to add a new DT_MACHINE_START() for the Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: use altera_a10_dt_match for the A10 machine desc
Diffstat (limited to 'arch/arm/mach-socfpga/core.h')
| -rw-r--r-- | arch/arm/mach-socfpga/core.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 7259c3732702..5bc6ea87cdf7 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -25,6 +25,7 @@ #define SOCFPGA_RSTMGR_MODPERRST 0x14 #define SOCFPGA_RSTMGR_BRGMODRST 0x1c +#define SOCFPGA_A10_RSTMGR_CTRL 0xC #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 /* System Manager bits */ |