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author | Christoffer Dall <christoffer.dall@linaro.org> | 2014-09-28 16:04:26 +0200 |
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committer | Christoffer Dall <christoffer.dall@linaro.org> | 2014-10-16 10:57:41 +0200 |
commit | 2df36a5dd6792870bef48f63bfca42055ea5b79c (patch) | |
tree | ef822d51fb8cd4adb030eab48c7dab131b632461 /arch/arm/mach-rpc | |
parent | 3d08c629244257473450a8ba17cb8184b91e68f8 (diff) | |
download | linux-2df36a5dd6792870bef48f63bfca42055ea5b79c.tar.bz2 |
arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs
The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
store these as an array of two such registers on the vgic vcpu struct.
However, we access them as a single 64-bit value or as a bitmap pointer
in the generic vgic code, which breaks BE support.
Instead, store them as u64 values on the vgic structure and do the
word-swapping in the assembly code, which already handles the byte order
for BE systems.
Tested-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm/mach-rpc')
0 files changed, 0 insertions, 0 deletions