diff options
| author | Tomeu Vizoso <tomeu.vizoso@collabora.com> | 2015-01-23 12:03:31 +0100 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-02-02 14:23:42 -0800 |
| commit | 1c8e600440c7f5036bd9a94526d01e9c7cb68dca (patch) | |
| tree | 36c9811e976332bc23a00a6fb216dce5e6b55a5a /arch/arm/mach-omap2 | |
| parent | b09d6d99102504a929cfaba4cd0e07658d7f01d1 (diff) | |
| download | linux-1c8e600440c7f5036bd9a94526d01e9c7cb68dca.tar.bz2 | |
clk: Add rate constraints to clocks
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.
Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
migrated clk-private.h changes to clk.c]
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/dpll3xxx.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/dpll44xx.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 49752d77f5bc..44e57ec225d4 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -473,6 +473,8 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw) * in failure. */ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long min_rate, + unsigned long max_rate, unsigned long *best_parent_rate, struct clk_hw **best_parent_clk) { diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 0e58e5a85d53..acacb900a58b 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -222,6 +222,8 @@ out: * in failure. */ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long min_rate, + unsigned long max_rate, unsigned long *best_parent_rate, struct clk_hw **best_parent_clk) { |