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authorArnd Bergmann <arnd@arndb.de>2016-03-02 23:32:24 +0100
committerArnd Bergmann <arnd@arndb.de>2016-03-02 23:32:24 +0100
commit3fcb230d14b031a6c3b26e8da56e062574b3e68d (patch)
tree8d49b5e0582f3b9815bff893c58f544d507286ab /arch/arm/mach-omap2
parentf3a186fbfd413f2453c511da2dbcdc594c87dbde (diff)
parente80499190db2fd752a60468f0fa462f87f993d49 (diff)
downloadlinux-3fcb230d14b031a6c3b26e8da56e062574b3e68d.tar.bz2
Merge tag 'omap-for-v4.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
Merge "omap soc changes for v4.6 merge window" from Tony Lindgren: SoC related changes for omaps for v4.6 merge window: - Enable runtime revision detection for dra7 to avoid multiple dts files for various variants - Add dma_slave_map for omap1/2/3 legacy mode booting - Add RTC interconnect target data for ti81xx and am43x - Add custom reset handler for PCIeSS - Add eDMA interconnect target data for dra7 * tag 'omap-for-v4.6/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 ARM: OMAP2+: Add rtc hwmod configuration for ti81xx ARM: DRA7: hwmod: Add custom reset handler for PCIeSS ARM: OMAP2+: DMA: Provide dma_slave_map to omap-dma for legacy boot ARM: OMAP1: DMA: Provide dma_slave_map to omap-dma ARM: OMAP: DRA7: Make use of omap_revision information for soc_is* calls ARM: AM43XX: hwmod: Add rtc hwmod ARM: DRA7: hwmod: Add reset data for PCIe ARM: DRA7: hwmod: Fix OCP2SCP sysconfig ARM: OMAP2+: hwmod data: Add SSI data for omap36xx
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/dma.c117
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c13
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c14
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c129
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_81xx_data.c38
-rw-r--r--arch/arm/mach-omap2/prm7xx.h1
-rw-r--r--arch/arm/mach-omap2/soc.h23
7 files changed, 323 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 1ed4be184a29..e58c13a9bea5 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -28,6 +28,7 @@
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
#include <linux/of.h>
#include <linux/omap-dma.h>
@@ -203,6 +204,108 @@ static unsigned configure_dma_errata(void)
return errata;
}
+static const struct dma_slave_map omap24xx_sdma_map[] = {
+ { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
+ { "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
+ { "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
+ { "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
+ { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
+ { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
+ { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
+ { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
+ { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
+ { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
+ { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
+ { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
+ { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
+ { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
+ { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
+ { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
+ { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
+ { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
+ { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
+ { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
+ { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
+ { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
+ { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
+ { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
+ { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
+ { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
+ { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
+ { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
+ { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
+ { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
+ { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
+ { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
+ { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
+ { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
+ { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
+ { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
+ { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
+ { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
+ { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
+ { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
+ { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
+ { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
+ { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
+ { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
+};
+
+static const struct dma_slave_map omap3xxx_sdma_map[] = {
+ { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
+ { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
+ { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
+ { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
+ { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
+ { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
+ { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
+ { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
+ { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
+ { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
+ { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
+ { "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
+ { "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
+ { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
+ { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
+ { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
+ { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
+ { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
+ { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
+ { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
+ { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
+ { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
+ { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
+ { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
+ { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
+ { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
+ { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
+ { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
+ { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
+ { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
+ { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
+ { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
+ { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
+ { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
+ { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
+ { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
+ { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
+ { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
+ { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
+ { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
+ { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
+ { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
+ { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
+ { "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
+ { "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
+ { "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
+ { "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
+ { "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
+ { "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
+ { "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
+ { "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
+ { "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
+};
+
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
.reg_map = reg_map,
.channel_stride = 0x60,
@@ -231,6 +334,20 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
p.errata = configure_dma_errata();
+ if (!of_have_populated_dt()) {
+ if (soc_is_omap24xx()) {
+ p.slave_map = omap24xx_sdma_map;
+ p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
+ } else if (soc_is_omap34xx() || soc_is_omap3630()) {
+ p.slave_map = omap3xxx_sdma_map;
+ p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
+ } else {
+ pr_err("%s: The legacy DMA map is not provided!\n",
+ __func__);
+ return -ENODEV;
+ }
+ }
+
pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
if (IS_ERR(pdev)) {
pr_err("%s: Can't build omap_device for %s:%s.\n",
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 0a985325cd64..9869a75c5d96 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3583,14 +3583,14 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1,
};
-static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
+static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
.name = "ssi",
.sysc = &omap34xx_ssi_sysc,
};
-static struct omap_hwmod omap34xx_ssi_hwmod = {
+static struct omap_hwmod omap3xxx_ssi_hwmod = {
.name = "ssi",
- .class = &omap34xx_ssi_hwmod_class,
+ .class = &omap3xxx_ssi_hwmod_class,
.clkdm_name = "core_l4_clkdm",
.main_clk = "ssi_ssr_fck",
.prcm = {
@@ -3605,9 +3605,9 @@ static struct omap_hwmod omap34xx_ssi_hwmod = {
};
/* L4 CORE -> SSI */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
.master = &omap3xxx_l4_core_hwmod,
- .slave = &omap34xx_ssi_hwmod,
+ .slave = &omap3xxx_ssi_hwmod,
.clk = "ssi_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3760,7 +3760,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_sad2d__l3,
&omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva,
- &omap34xx_l4_core__ssi,
+ &omap3xxx_l4_core__ssi,
NULL
};
@@ -3784,6 +3784,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_sad2d__l3,
&omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva,
+ &omap3xxx_l4_core__ssi,
NULL
};
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index e97a894b5f88..97fd399202dc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -1020,9 +1020,21 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
NULL,
};
+static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
+ &am33xx_l4_wkup__rtc,
+ NULL,
+};
+
int __init am43xx_hwmod_init(void)
{
+ int ret;
+
omap_hwmod_am43xx_reg();
omap_hwmod_init();
- return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
+ ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
+
+ if (!ret && of_machine_is_compatible("ti,am4372"))
+ ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
+
+ return ret;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 848356e38b74..9442d89bd229 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -430,6 +430,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
};
/*
+ * 'tpcc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+static struct omap_hwmod dra7xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &dra7xx_tpcc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'tptc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+ .name = "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod dra7xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod dra7xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
* 'dss' class
*
*/
@@ -1482,8 +1543,7 @@ static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
@@ -1527,19 +1587,49 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
*
*/
+/*
+ * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
+ * functionality of OMAP HWMOD layer does not deassert the hardreset lines
+ * associated with an IP automatically leaving the driver to handle that
+ * by itself. This does not work for PCIeSS which needs the reset lines
+ * deasserted for the driver to start accessing registers.
+ *
+ * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
+ * lines after asserting them.
+ */
+static int dra7xx_pciess_reset(struct omap_hwmod *oh)
+{
+ int i;
+
+ for (i = 0; i < oh->rst_lines_cnt; i++) {
+ omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
+ omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
+ }
+
+ return 0;
+}
+
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
.name = "pcie",
+ .reset = dra7xx_pciess_reset,
};
/* pcie1 */
+static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
+ { .name = "pcie", .rst_shift = 0 },
+};
+
static struct omap_hwmod dra7xx_pciess1_hwmod = {
.name = "pcie1",
.class = &dra7xx_pciess_hwmod_class,
.clkdm_name = "pcie_clkdm",
+ .rst_lines = dra7xx_pciess1_resets,
+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
@@ -1547,14 +1637,22 @@ static struct omap_hwmod dra7xx_pciess1_hwmod = {
};
/* pcie2 */
+static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
+ { .name = "pcie", .rst_shift = 1 },
+};
+
+/* pcie2 */
static struct omap_hwmod dra7xx_pciess2_hwmod = {
.name = "pcie2",
.class = &dra7xx_pciess_hwmod_class,
.clkdm_name = "pcie_clkdm",
+ .rst_lines = dra7xx_pciess2_resets,
+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
.main_clk = "l4_root_clk_div",
.prcm = {
.omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
@@ -2549,6 +2647,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main_1 -> tpcc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_tpcc_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc0 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_tptc0_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_tptc1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
{
.name = "family",
@@ -3366,6 +3488,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__mcasp3,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
+ &dra7xx_l3_main_1__tpcc,
+ &dra7xx_l3_main_1__tptc0,
+ &dra7xx_l3_main_1__tptc1,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_l3_main_1__hdmi,
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index e493ae372910..609e2397ea47 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -228,6 +228,42 @@ static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
.user = OCP_USER_MPU,
};
+/* RTC */
+static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
+ .rev_offs = 0x74,
+ .sysc_offs = 0x78,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = SIDLE_FORCE | SIDLE_NO |
+ SIDLE_SMART | SIDLE_SMART_WKUP,
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
+ .name = "rtc",
+ .sysc = &ti81xx_rtc_sysc,
+};
+
+struct omap_hwmod ti81xx_rtc_hwmod = {
+ .name = "rtc",
+ .class = &ti81xx_rtc_hwmod_class,
+ .clkdm_name = "alwon_l3s_clkdm",
+ .flags = HWMOD_NO_IDLEST,
+ .main_clk = "sysclk18_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
+ .master = &dm81xx_l4_ls_hwmod,
+ .slave = &ti81xx_rtc_hwmod,
+ .clk = "sysclk6_ck",
+ .user = OCP_USER_MPU,
+};
+
/* UART common */
static struct omap_hwmod_class_sysconfig uart_sysc = {
.rev_offs = 0x50,
@@ -1376,6 +1412,7 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__mcspi1,
&dm814x_l4_ls__mmc1,
&dm814x_l4_ls__mmc2,
+ &ti81xx_l4_ls__rtc,
&dm81xx_alwon_l3_fast__tpcc,
&dm81xx_alwon_l3_fast__tptc0,
&dm81xx_alwon_l3_fast__tptc1,
@@ -1415,6 +1452,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__gpio1,
&dm81xx_l4_ls__gpio2,
&dm81xx_l4_ls__elm,
+ &ti81xx_l4_ls__rtc,
&dm816x_l4_ls__mmc1,
&dm816x_l4_ls__timer1,
&dm816x_l4_ls__timer2,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index cc1e6a2b97f6..294deed956f3 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -360,6 +360,7 @@
/* PRM.L3INIT_PRM register offsets */
#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010
#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 79ca3c3eb2af..70df8f6cddcc 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -181,6 +181,14 @@ static inline int is_ti ##class (void) \
return (GET_TI_CLASS == (id)) ? 1 : 0; \
}
+#define GET_DRA_CLASS ((omap_rev() >> 24) & 0xff)
+
+#define IS_DRA_CLASS(class, id) \
+static inline int is_dra ##class (void) \
+{ \
+ return (GET_DRA_CLASS == (id)) ? 1 : 0; \
+}
+
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
@@ -201,6 +209,12 @@ static inline int is_am ##subclass (void) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_SUBCLASS(subclass, id) \
+static inline int is_dra ##subclass (void) \
+{ \
+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
+}
+
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
@@ -210,6 +224,7 @@ IS_AM_CLASS(33xx, 0x33)
IS_AM_CLASS(43xx, 0x43)
IS_TI_CLASS(81xx, 0x81)
+IS_DRA_CLASS(7xx, 0x7)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
@@ -224,6 +239,8 @@ IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
IS_AM_SUBCLASS(437x, 0x437)
+IS_DRA_SUBCLASS(75x, 0x75)
+IS_DRA_SUBCLASS(72x, 0x72)
#define soc_is_omap24xx() 0
#define soc_is_omap242x() 0
@@ -397,9 +414,9 @@ IS_OMAP_TYPE(3430, 0x3430)
#undef soc_is_dra7xx
#undef soc_is_dra74x
#undef soc_is_dra72x
-#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
-#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
-#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
+#define soc_is_dra7xx() is_dra7xx()
+#define soc_is_dra74x() is_dra75x()
+#define soc_is_dra72x() is_dra72x()
#endif
/* Various silicon revisions for omap2 */