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author | Linus Walleij <linus.walleij@linaro.org> | 2015-01-20 11:03:07 +0100 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2015-01-20 11:03:07 +0100 |
commit | ee65ef609aa81539ac3792df88f04bfe29a77546 (patch) | |
tree | 6816eaa3d45fa1078408f2ccfa5f88d32733d1d9 /arch/arm/mach-omap2/omap-headsmp.S | |
parent | 7a839e9a277d4a410a9b015d561ff09739bc0ff6 (diff) | |
parent | ec6f34e5b552fb0a52e6aae1a5afbbb1605cc6cc (diff) | |
download | linux-ee65ef609aa81539ac3792df88f04bfe29a77546.tar.bz2 |
Merge tag 'v3.19-rc5' into devel
Linux 3.19-rc5
Diffstat (limited to 'arch/arm/mach-omap2/omap-headsmp.S')
-rw-r--r-- | arch/arm/mach-omap2/omap-headsmp.S | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4993d4bfe9b2..6d1dffca6c7b 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -22,6 +22,7 @@ /* Physical address needed since MMU not enabled yet on secondary core */ #define AUX_CORE_BOOT0_PA 0x48281800 +#define API_HYP_ENTRY 0x102 /* * OMAP5 specific entry point for secondary CPU to jump from ROM @@ -41,6 +42,26 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 b secondary_startup ENDPROC(omap5_secondary_startup) /* + * Same as omap5_secondary_startup except we call into the ROM to + * enable HYP mode first. This is called instead of + * omap5_secondary_startup if the primary CPU was put into HYP mode by + * the boot loader. + */ +ENTRY(omap5_secondary_hyp_startup) +wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 + ldr r0, [r2] + mov r0, r0, lsr #5 + mrc p15, 0, r4, c0, c0, 5 + and r4, r4, #0x0f + cmp r0, r4 + bne wait_2 + ldr r12, =API_HYP_ENTRY + adr r0, hyp_boot + smc #0 +hyp_boot: + b secondary_startup +ENDPROC(omap5_secondary_hyp_startup) +/* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which * secondary core is held until we're ready for it to initialise. |