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author | Paul Walmsley <paul@pwsan.com> | 2012-09-14 23:18:20 -0600 |
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committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 19:10:18 -0700 |
commit | 7a2bd1cc3926327c0393deb52e8300af75b1c9e1 (patch) | |
tree | 0e075412a394f2de3270104e2689f39cfda18a5c /arch/arm/mach-omap2/clock2xxx.h | |
parent | ed1ebc4948fdfe4c68865e5543b4a68e5a55973b (diff) | |
download | linux-7a2bd1cc3926327c0393deb52e8300af75b1c9e1.tar.bz2 |
ARM: OMAP2xxx: clock: add APLL rate recalculation functions
OMAP2420 and OMAP2430 chips each have two on-chip APLLs. When locked,
one APLL generates a 96 MHz rate; the other, a 54 MHz rate.
Previously we treated these clocks as fixed-rate clocks at the locked
rates, but this isn't quite right. The locked rate should be returned
when the APLL is locked, and a zero rate should be returned when the
APLL is stopped. This patch adds the infrastructure that will be used
by the CCF changes.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock2xxx.h')
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index 58581511d795..82147c49a8de 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h @@ -27,6 +27,10 @@ unsigned long omap2_dpllcore_recalc(struct clk_hw *hw, int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate, unsigned long parent_rate); void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); +unsigned long omap2_clk_apll54_recalc(struct clk_hw *hw, + unsigned long parent_rate); +unsigned long omap2_clk_apll96_recalc(struct clk_hw *hw, + unsigned long parent_rate); #else unsigned long omap2_table_mpu_recalc(struct clk *clk); int omap2_select_table_rate(struct clk *clk, unsigned long rate); |