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author | David S. Miller <davem@davemloft.net> | 2011-11-21 13:50:33 -0500 |
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committer | David S. Miller <davem@davemloft.net> | 2011-11-21 13:50:33 -0500 |
commit | efd0bf97deeddd9ba53daabfc470a1399c6b0b2d (patch) | |
tree | eec56da5fbc796bac7c67f1990a18f5e0a304059 /arch/arm/mach-imx/clock-imx6q.c | |
parent | f8a15af093b19b86d56933c8757cee298d0f32a8 (diff) | |
parent | 6fe4c6d466e95d31164f14b1ac4aefb51f0f4f82 (diff) | |
download | linux-efd0bf97deeddd9ba53daabfc470a1399c6b0b2d.tar.bz2 |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
The forcedeth changes had a conflict with the conversion over
to atomic u64 statistics in net-next.
The libertas cfg.c code had a conflict with the bss reference
counting fix by John Linville in net-next.
Conflicts:
drivers/net/ethernet/nvidia/forcedeth.c
drivers/net/wireless/libertas/cfg.c
Diffstat (limited to 'arch/arm/mach-imx/clock-imx6q.c')
-rw-r--r-- | arch/arm/mach-imx/clock-imx6q.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index e0b926dfeced..613a1b993bff 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -1139,7 +1139,7 @@ static int _clk_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; max_div = ((d->bm_pred >> d->bp_pred) + 1) * - ((d->bm_pred >> d->bp_pred) + 1); + ((d->bm_podf >> d->bp_podf) + 1); div = parent_rate / rate; if (div == 0) @@ -2002,6 +2002,21 @@ int __init mx6q_clocks_init(void) clk_set_rate(&asrc_serial_clk, 1500000); clk_set_rate(&enfc_clk, 11000000); + /* + * Before pinctrl API is available, we have to rely on the pad + * configuration set up by bootloader. For usdhc example here, + * u-boot sets up the pads for 49.5 MHz case, and we have to lower + * the usdhc clock from 198 to 49.5 MHz to match the pad configuration. + * + * FIXME: This is should be removed after pinctrl API is available. + * At that time, usdhc driver can call pinctrl API to change pad + * configuration dynamically per different usdhc clock settings. + */ + clk_set_rate(&usdhc1_clk, 49500000); + clk_set_rate(&usdhc2_clk, 49500000); + clk_set_rate(&usdhc3_clk, 49500000); + clk_set_rate(&usdhc4_clk, 49500000); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); base = of_iomap(np, 0); WARN_ON(!base); |