diff options
| author | Rob Herring <rob.herring@calxeda.com> | 2012-03-01 20:48:12 -0600 |
|---|---|---|
| committer | Rob Herring <rob.herring@calxeda.com> | 2012-07-26 09:09:59 -0500 |
| commit | 8ef6e6201b26cb9fde79c1baa08145af6aca2815 (patch) | |
| tree | c2ae90128bfea1a6ff8d463141b1a14ab1b1faf6 /arch/arm/mach-footbridge/dc21285.c | |
| parent | c04dc9a6bfe88b8c15bf8dd298fc24d6b9df3f22 (diff) | |
| download | linux-8ef6e6201b26cb9fde79c1baa08145af6aca2815.tar.bz2 | |
ARM: footbridge: use fixed PCI i/o mapping
Move footbridge PCI to fixed i/o mapping. io.h is still needed for the
!MMU case.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-footbridge/dc21285.c')
| -rw-r--r-- | arch/arm/mach-footbridge/dc21285.c | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 9d62e3381024..a7cd2cf5e08d 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = DC21285_PCI_MEM; - pci_add_resource_offset(&sys->resources, - &ioport_resource, sys->io_offset); + pci_ioremap_io(0, DC21285_PCI_IO); + pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); @@ -298,7 +298,7 @@ void __init dc21285_preinit(void) mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) if (mem_mask >= mem_size) - break; + break; /* * These registers need to be set up whether we're the @@ -350,14 +350,6 @@ void __init dc21285_preinit(void) "PCI data parity", NULL); if (cfn_mode) { - static struct resource csrio; - - csrio.flags = IORESOURCE_IO; - csrio.name = "Footbridge"; - - allocate_resource(&ioport_resource, &csrio, 128, - 0xff00, 0xffff, 128, NULL, NULL); - /* * Map our SDRAM at a known address in PCI space, just in case * the firmware had other ideas. Using a nonzero base is @@ -365,7 +357,7 @@ void __init dc21285_preinit(void) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). */ *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = csrio.start; + *CSR_PCICSRIOBASE = 0; *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); *CSR_PCIROMBASE = 0; *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |