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| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-20 09:46:42 +0000 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-22 13:46:18 +0000 |
| commit | 33625282adaaba93d37aa437ae9688bf0cc024a9 (patch) | |
| tree | 3cfda95aa133f0ff49d11bf5682647eb4faec367 /arch/arm/include | |
| parent | 66569052fe5328729ff696c1ec17913907d00b5f (diff) | |
| download | linux-33625282adaaba93d37aa437ae9688bf0cc024a9.tar.bz2 | |
irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn
We would like to reset the Group-0 Active Priority Registers
at boot time if they are available to us. They would be available
if SCR_EL3.FIQ was not set, but we cannot directly probe this bit,
and short of checking, we may end-up trapping to EL3, and the
firmware may not be please to get such an exception. Yes, this
is dumb.
Instead, let's use PMR to find out if its value gets affected by
SCR_EL3.FIQ being set. We use the fact that when SCR_EL3.FIQ is
set, the LSB of the priority is lost due to the shifting back and
forth of the actual priority. If we read back a 0, we know that
Group0 is unavailable. In case we read a non-zero value, we can
safely reset the AP0Rn register.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch_gicv3.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h index 27288bdbd840..0bd530702118 100644 --- a/arch/arm/include/asm/arch_gicv3.h +++ b/arch/arm/include/asm/arch_gicv3.h @@ -137,6 +137,7 @@ static inline u64 read_ ## a64(void) \ return val; \ } +CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) @@ -206,11 +207,6 @@ static inline u32 gic_read_iar(void) return irqstat; } -static inline void gic_write_pmr(u32 val) -{ - write_sysreg(val, ICC_PMR); -} - static inline void gic_write_ctlr(u32 val) { write_sysreg(val, ICC_CTLR); |